# Pedal Parts / DIY

CMOS - CD4007, Dual Complementary Pair Plus Inverter, 14-Pin DIP
CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. Features:
• Standardized symmetrical output characteristics
• Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No.
$0.75 CMOS - CD4052, 4:1, 2-Channel General-Purpose Multiplexer, 16-Pin DIP The CD4052B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.$0.89
CMOS - CD4013, Dual D-Type Flip-Flop, 14-Pin DIP
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse.
$0.75 CMOS - CD4066, Quad Bilateral Switch, 14-Pin DIP The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B device consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off).$0.59
CMOS - CD4016, Quad Bilateral Switch, 14-Pin DIP
CD4016B Series types are quad bilateral switches intended for the transmission or multiplexing of analog or digital signals. Each of the four independent bilateral switches has a single control signal input which simultaneously biases both the p and n device in a given switch on or off. Features:
• 20-V digital or ± 10-V peak-to-peak switching
• 280- typical on-state resistance for 15-V operation
• Switch on-state resistance matched to within 10 typ. over 15-V signal-input range
• High on/off output-voltage ratio: 65 dB typ. @ fis = 10 kHz, RL = 10 k
• High degree of linearity: <0.5% distortion typ. @ fis = 1 kHz, Vis = 5 Vp-p, VDD–VSS
• Extremely low off-state switch leakage resulting in very low offset current and high effective off-state resistance: 100pA typ.
$0.65 CMOS - CD4070, Quad XOR (Exclusive-OR) Gates, 14-Pin DIP The CD4070B contains four independent Exclusive-OR gates. The CD4070B provides the system designer with a means for direct implementation of the Exclusive-OR functions, respectively. Features: • High-Voltage Types (20V Rating) • CD4070B - Quad Exclusive-OR Gate • Medium Speed Operation • tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range • 100nA at 18V and 25°C • Noise Margin (Over Full Package Temperature Range) • 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No.$0.95
CMOS - CD4021, 8-Stage Static Shift Register, 16-Pin DIP
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.
$0.95 CMOS - CD4077, Quad XNOR (Exclusive-NOR) Gates, 14-Pin DIP The CD4077B contains four independent Exclusive-NOR gates. The CD4077B provides the system designer with a means for direct implementation of the Exclusive-NOR functions, respectively. Features: • High-Voltage Types (20V Rating) • CD4077B - Quad Exclusive-NOR Gate • Medium Speed Operation • tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range • 100nA at 18V and 25°C • Noise Margin (Over Full Package Temperature Range) • 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No.$1.15
CMOS - CD4027, Dual J-K Flip-Flop, 16-Pin DIP
CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the CD4013B dual D-type flip-flop. The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse.
$0.65 CMOS - CD4093, Quad 2-Input NAND Schmitt Triggers, 14-Pin DIP CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH). Features: • Schmitt-trigger action on each input with no external components • Hysteresis voltage typically 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V • Noise immunity greater than 50% • No limit on input rise and fall times • Standardized, symmetrical output characteristics • 100% tested for quiescent current at 20 V • Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C • 5-V, 10-V, and 15-V parametric ratings • Meets all requirements of JEDEC Tentative Standard No.$0.75
CMOS - CD4030, Quad XOR (Exclusive-OR) Gate, 14-Pin DIP
CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. Features:
• Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =
• 1 V at VDD = 5 V
• 2 V at VDD = 10 V
• 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No.
$1.15 CMOS - CD40106, Hex Schmitt-Trigger Inverters, 14-Pin DIP The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). Features: • Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): • 0.9 V at VDD = 5 V • 2.3 V at VDD = 10 V • 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at 20 V • Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: 100 nA at 18 V and 25°C • Low VDD and VSS Current During Slow Input Ramp • 5-V, 10-V, and 15-V Parametric Ratings$0.75
CMOS - CD4046, Micropower Phase-Locked Loop, 16-Pin DIP
CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:
• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
• Exclusive-OR network (I)
• Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: <1% (typ.) at VDD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod.
$1.29 CMOS - CD4049, Hex Inverting Buffer and Converter, 16-Pin DIP The CD4049UB devices are inverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features: • Inverting • High Sink Current for Driving 2 TTL Loads • High-to-Low Level Logic Conversion • 100% Tested for Quiescent Current at 20 V • Maximum Input Current of 1 µA at 18 V Over Full • Package Temperature Range; 100 nA at 18 V and 25°C • 5-V, 10-V, and 15-V Parametric Ratings Applications • CMOS to DTL or TTL Hex Converters • CMOS Current Sink or Source Drivers • CMOS High-to-Low Logic Level Converters$0.75
CMOS - CD4001, Quad 2-Input NOR Gate, 14-Pin DIP
CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates. Features:
• Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings
$0.75 CMOS - CD4051, 8:1, 1-Channel Analog Multiplexer with Logic-Level Conversion, 16-Pin DIP The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.$0.99
CMOS - CD4011, 2-Input CMOS NAND Gates, 14-Pin DIP
CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Features:
• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
• 1 V at VDD = 5 V
• 2 V at VDD = 10 V
• 2.5 at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"
$0.75 CMOS - CD4053, 2:1 SPDT, 3-Channel Analog Multiplexer with Logic-Level Conversion, 16-Pin DIP The CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.$0.75
CMOS - CD4015, Dual 4-Stage Static Shift Register, 16-Pin DIP
CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line.
$0.75 CMOS - CD4069, Hex Inverter, 14-Pin DIP The CD4069UB device consists of six CMOS inverter circuits. These devices are intended for all general-purpose inverter applications where the medium-power TTL-drive and logic-level-conversion capabilities of circuits such as the CD4009 and CD4049 hex inverter and buffers are not required. Features: • Standardized symmetrical output characteristics • Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical) • 100% Tested for quiescent current at 20 V • Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C • Meets all requirements of JEDEC tentative standard No. 13B, Standard Specifications for Description of B Series CMOS Devices$1.15
CMOS - CD4017, CMOS Decade Counter, 16-Pin DIP
CD4017B is a 5-stage Johnson counter having 10 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle.
$0.55 CMOS - CD4071, Quad 2-Input OR Gates, 14-Pin DIP CD4071B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. Features: • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V • 100% tested for quiescent current at 20 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Standardized, symmetrical output characteristics • Noise margin (full package-temperature range): • 1 V at VDD = 5 V • 2 V at VDD = 10 V • 2.5 V at VDD = 15 V • 5-V, 10-V, and 15-V parametric ratings • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"$0.95
CMOS - CD4024, 7-Stage Ripple-Carry Binary Counter/Divider, 14-Pin DIP
CD4024B is a 7-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.
$1.15 CMOS - CD4081, Quad 2-Input AND Gates, 14-Pin DIP CD4081B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features: • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V • 100% tested for quiescent current at 20 V • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C • Noise margin (full package-temperature range) = • 1 V at VDD = 5 V • 2 V at VDD = 10 V • 2.5 V at VDD = 15 V • Standardized, symmetrical output characteristics • 5-V, 10-V, and 15-V parametric ratings • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"$1.26
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