Pedal Parts / DIY

Premium 9V battery clip with a rigid plastic frame and I-style wire orientation. This high quality battery snap features nickel-plated phosphor bronze contacts. The six inch leads are 26 AWG stranded wire, prestripped and tinned for an easy installation.

This is a set of two 2N1309 germanium transistors that have been hand-selected to work in the germanium Fuzz Face circuit. Also included are 4 metal film resistors to use in the circuit. In most cases, the values have been modified from the stock values slightly to ensure that the collector of Q2 biases to roughly -4.5V. A data sheet containing the schematic and the resistor values is included so that you can use your own resistor type if you would prefer. There is a range of bias voltages that can sound nice in a Fuzz Face, and voltages in original units varied. These transistors have been tested with bias voltage, sound, and noise level in mind. Note that due to a variety of factors such as battery/PSU voltage, temperature, and component tolerance, the voltage on the collector of Q2 may not measure at exactly -4.5V, but it should be close in a properly-built circuit.

Prewired steel low-profile LED bezel with a diffused LED. With a 0.061” height, this steel LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and rubber o-ring included.

Prewired low-profile LED bezel with a diffused LED. With a 0.07” height, this black metal LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and rubber o-ring included.

Prewired cone-shaped LED bezel. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and lock washer included.

Self adhesive metal cable clips. They easily attach to most surfaces using a strong foam adhesive. These cable clips are a great way to tidy up project wiring and securing components.

2N5457 N-Channel JFET in a TO-92 package. The 2N5457 is designed primarily for audio and switching applications.

• Max drain to gate voltage = 25 V
• Max gate to source voltage = -25 V
• Max forward gate current = 10 mA

The CD4050B devices are noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features:

• Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
• Package Temperature Range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V Parametric Ratings

Applications

• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. Features:

• Standardized symmetrical output characteristics
• Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No.

The CD4052B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse.

The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B device consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off).

CD4016B Series types are quad bilateral switches intended for the transmission or multiplexing of analog or digital signals. Each of the four independent bilateral switches has a single control signal input which simultaneously biases both the p and n device in a given switch on or off. Features:

• 20-V digital or ± 10-V peak-to-peak switching
• 280- typical on-state resistance for 15-V operation
• Switch on-state resistance matched to within 10 typ. over 15-V signal-input range
• High on/off output-voltage ratio: 65 dB typ. @ fis = 10 kHz, RL = 10 k
• High degree of linearity: <0.5% distortion typ. @ fis = 1 kHz, Vis = 5 Vp-p, VDD–VSS
• Extremely low off-state switch leakage resulting in very low offset current and high effective off-state resistance: 100pA typ.

The CD4070B contains four independent Exclusive-OR gates. The CD4070B provides the system designer with a means for direct implementation of the Exclusive-OR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.

The CD4077B contains four independent Exclusive-NOR gates. The CD4077B provides the system designer with a means for direct implementation of the Exclusive-NOR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the CD4013B dual D-type flip-flop. The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse.

CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-trigger action on each input with no external components
• Hysteresis voltage typically 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V
• Noise immunity greater than 50%
• No limit on input rise and fall times
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No.

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. Features:

• Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No.

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-Trigger Inputs
• Hysteresis Voltage (Typical):
  
  • 0.9 V at VDD = 5 V
  • 2.3 V at VDD = 10 V
  • 3.5 V at VDD = 15 V
• Noise Immunity Greater Than 50%
• No Limit On Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• For Quiescent Current at 20 V
• Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: 100 nA at 18 V and 25°C
• Low VDD and VSS Current During Slow Input Ramp
• 5-V, 10-V, and 15-V Parametric Ratings

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:

• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
  
  • Exclusive-OR network (I)
  • Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: <1% (typ.) at VDD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod.

The CD4049UB devices are inverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features:

• Inverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
• Package Temperature Range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V Parametric Ratings

Applications

• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates. Features:

• Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V parametric ratings

The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.