New Products

Black Marshall-style knobs with a silver cap. This is the taller 0.766” version of this knob. The silver cap has no indicator line matching those found on vintage fuzz pedals such as the Supa Fuzz, Tone Bender Professional MKII, Shatterbox, and MKIII and MKIV Tone Benders. Fits ¼" shaft pots using a slotted set screw.

• Height: 0.766 in.
• Top Diameter:0.594 in.
• Bottom Diameter:0.766 in.
• Fits ¼" shaft with set screw

Keyed washer for use with mini toggle switches. These nickel plated washers work on any 1/4-40 UNS threaded bushing with a vertical key slot. A small anti-rotation tab is on the outer edge of this flat washer. These are the same as the stock washers included with Carling mini toggle switches.

Hex nuts for use with mini toggle switches. These nickel plated dress nuts work on any 1/4-40 UNS threaded bushing. These are the same as the stock nuts included with Carling mini toggle switches.

Premium 9V battery clip with a rigid plastic frame and I-style wire orientation. This high quality battery snap features nickel-plated phosphor bronze contacts. The six inch leads are 26 AWG stranded wire, prestripped and tinned for an easy installation.

Piher PT-15 15mm carbon trimmer potentiometers. These trimmers are used in a variety of amps and equipment and most notably in Marshall amplifiers. Features:

• Carbon resistive element
• Dust proof enclosure
• Polyester substrate

25kΩ Piher PT-15 15mm carbon trimmer potentiometers. These trimmers are used in a variety of amps and equipment and mount horizontally to the PCB with a slotted top adjustment. Features:

• Carbon resistive element
• Dust proof enclosure
• Polyester substrate

This is a set of two 2N1309 germanium transistors that have been hand-selected to work in the germanium Fuzz Face circuit. Also included are 4 metal film resistors to use in the circuit. In most cases, the values have been modified from the stock values slightly to ensure that the collector of Q2 biases to roughly -4.5V. A data sheet containing the schematic and the resistor values is included so that you can use your own resistor type if you would prefer. There is a range of bias voltages that can sound nice in a Fuzz Face, and voltages in original units varied. These transistors have been tested with bias voltage, sound, and noise level in mind. Note that due to a variety of factors such as battery/PSU voltage, temperature, and component tolerance, the voltage on the collector of Q2 may not measure at exactly -4.5V, but it should be close in a properly-built circuit.

CE Manufacturing USA Made Multi Section Can Capacitor. Reproduced To Exact Mallory Specs Using Original Mallory Machinery.

• 2 sections - 40/40µF at 450V
• -10%, +50% tolerance
• 85° temperature rating
• 1-⅜" dia. x 2.6" tall

Prewired cone-shaped LED bezel. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12VDC. Mounting nut and lock washer included.

Prewired steel low-profile LED bezel with a diffused LED. With a 0.061” height, this steel LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12VDC. Mounting nut and rubber o-ring included.

Self adhesive metal cable clips. They easily attach to most surfaces using a strong foam adhesive. These cable clips are a great way to tidy up project wiring and securing components.

Prewired low-profile LED bezel with a diffused LED. With a 0.07” height, this black metal LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12VDC. Mounting nut and rubber o-ring included.

MPF102 N-Channel JFET in a TO-92 package. The MPF102 is designed for electronic switching applications such as low ON resistance analog switching.

• Max drain to gate voltage = 25 V
• Max gate to source voltage = -25 V
• Max forward gate current = 10 mA

2N5457 N-Channel JFET in a TO-92 package. The 2N5457 is designed primarily for audio and switching applications.

• Max drain to gate voltage = 25 V
• Max gate to source voltage = -25 V
• Max forward gate current = 10 mA

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. Features:

• Standardized symmetrical output characteristics
• Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
• 100% tested for quiescent current at 20 V
• Meets all requirements of JEDEC Tentative Standard No.

The CD4077B contains four independent Exclusive-NOR gates. The CD4077B provides the system designer with a means for direct implementation of the Exclusive-NOR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.

CD4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q and OSCILLATOR. In all modes of operation, and external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals. Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode off operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gatable multivibrator.

The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

The CD4049UB devices are inverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features:

• Inverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
• Package Temperature Range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V Parametric Ratings

Applications

• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters

The CD4052B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low.

CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Features:

• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:

• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
  
  • Exclusive-OR network (I)
  • Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: <1% (typ.) at VDD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod.

CD4017B is a 5-stage Johnson counter having 10 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle.