New Products

Premium 9V battery clip with a rigid plastic frame and I-style wire orientation. This high quality battery snap features nickel-plated phosphor bronze contacts. The six inch leads are 26 AWG stranded wire, prestripped and tinned for an easy installation.

Piher PT-15 15mm carbon trimmer potentiometers. These trimmers are used in a variety of amps and equipment and most notably in Marshall amplifiers. Features:

• Carbon resistive element
• Dust proof enclosure
• Polyester substrate

25kΩ Piher PT-15 15mm carbon trimmer potentiometers. These trimmers are used in a variety of amps and equipment and mount horizontally to the PCB with a slotted top adjustment. Features:

• Carbon resistive element
• Dust proof enclosure
• Polyester substrate

This is a set of two 2N1309 germanium transistors that have been hand-selected to work in the germanium Fuzz Face circuit. Also included are 4 metal film resistors to use in the circuit. In most cases, the values have been modified from the stock values slightly to ensure that the collector of Q2 biases to roughly -4.5V. A data sheet containing the schematic and the resistor values is included so that you can use your own resistor type if you would prefer. There is a range of bias voltages that can sound nice in a Fuzz Face, and voltages in original units varied. These transistors have been tested with bias voltage, sound, and noise level in mind. Note that due to a variety of factors such as battery/PSU voltage, temperature, and component tolerance, the voltage on the collector of Q2 may not measure at exactly -4.5V, but it should be close in a properly-built circuit.

Prewired low-profile LED bezel with a diffused LED. With a 0.07” height, this black metal LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and rubber o-ring included.

Prewired cone-shaped LED bezel. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and lock washer included.

Prewired steel low-profile LED bezel with a diffused LED. With a 0.061” height, this steel LED bezel has an almost flush appearance on the panel it’s mounted to. An internal current limiting resistor is installed in this bezel and it can be used with voltages up to 12V. Mounting nut and rubber o-ring included.

Self adhesive metal cable clips. They easily attach to most surfaces using a strong foam adhesive. These cable clips are a great way to tidy up project wiring and securing components.

MPF102 N-Channel JFET in a TO-92 package. The MPF102 is designed for electronic switching applications such as low ON resistance analog switching.

• Max drain to gate voltage = 25 V
• Max gate to source voltage = -25 V
• Max forward gate current = 10 mA

2N5457 N-Channel JFET in a TO-92 package. The 2N5457 is designed primarily for audio and switching applications.

• Max drain to gate voltage = 25 V
• Max gate to source voltage = -25 V
• Max forward gate current = 10 mA

The CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B device consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 17, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off).

The CD4040B is a 12-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.

The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the CD4013B dual D-type flip-flop. The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse.

CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Features:

• Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.

CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high. Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast.

CD4024B is a 7-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.

CD4081B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features:

• Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse.

CD4071B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. Features:

• Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
  
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). Features:

• Schmitt-Trigger Inputs
• Hysteresis Voltage (Typical):
  
  • 0.9 V at VDD = 5 V
  • 2.3 V at VDD = 10 V
  • 3.5 V at VDD = 15 V
• Noise Immunity Greater Than 50%
• No Limit On Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• For Quiescent Current at 20 V
• Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: 100 nA at 18 V and 25°C
• Low VDD and VSS Current During Slow Input Ramp
• 5-V, 10-V, and 15-V Parametric Ratings

The CD4070B contains four independent Exclusive-OR gates. The CD4070B provides the system designer with a means for direct implementation of the Exclusive-OR functions, respectively. Features:

• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• Medium Speed Operation
• tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
• 100nA at 18V and 25°C
• Noise Margin (Over Full Package Temperature Range)
• 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No.