# Integrated Circuits

IC Socket - Dual in-line package, 2.54mm Pitch, 7.62mm Spacing
IC component sockets for dual in-line package chips (DIP, PDIP, DIL, DIPP.) These sockets feature ladder style cases with tinned stamped and formed connections.
Starting at $0.35 Integrated Circuit - PT2399, Echo / Delay PT2399 echo/delay chip used in many DIY and commercial pedals. The PT2399 is in a DIP 16 package. Minimal external components are required for use and delay time is set with resistance.$2.00
Integrated Circuit - AS3340A, VCO, Alfa, 16-Pin Dip
The AS3340A is Alfa’s version of the CEM3340 IC. The AS3340A is a completely self-contained, precision voltage controlled oscillator, featuring both exponential and linear control scales and up to four buffered output waveforms: triangle, sawtooth, square, and pulse with voltage controllable pulse width. Full temperature compensation makes these VCOs extremely stable, and eliminates the need for a temperature compensation resistor. The highly accurate exponential and linear control inputs are virtual ground summing nodes, allowing multiple control voltages to be mixed within the device itself.
Also included is provision for hard and soft synchronization of the frequency, and an output for easy adjustment of high frequency tracking. Special care in the design ensures oscillation start-up under any power-on sequence and supply conditions.
An on-chip 7.4 volt Zener diode allows the device to operate off ±15 volt supplies, as well as +12, -5 volt supplies.
$7.95 Integrated Circuit - AS3310, VC ADSR, Alfa, 16-Pin Dip The AS3310 is Alfa’s version of the CEM3310 IC. The AS3310 is a self-contained, precision ADSR type of envelope generator intended for electronic music and other sound generation applications. Attack, decay and release times are exponentially voltage controllable over a wide range, and the sustain level is linearly voltage controllable from 0 to 100% of the peak voltage Vp. All four control Inputs are Isolated from the rest of the circuitry so that the control pins of tracking units may be simply tied together. On the negative power output, there is an internal Zener diode at 7.4 volts ± 10%, which allows the chip to supply a maximum voltage of ± 15 volts with a current-limiting resistor REE, and a minimum positive supply voltage of + 11 volts and a minimum negative supply voltage of -5 volts.. A series current limiting resistor must be added between pin 6 and the supply.$5.85
OTA - AS3280, Dual, Linearizing Diodes, Alfa, 16-Pin DIP
The AS3280 is Alfa’s version of the CA3280 IC. The AS3280 consists of two variable operational amplifiers that are designed to substantially reduce the initial input offset voltage and the offset voltage variation with respect to changes in programming current. This design results in reduced "AGC thump," an objectionable characteristic of many AGC systems. Careful design of critical places of the circuit reduces the amplifier dependence upon thermal and processing variables.
The AS3280 has all the generic characteristics of an operational voltage amplifier except that the forward transfer characteristics is best described by transconductance rather than voltage gain, and the output is current, not voltage. The magnitude of the output current is equal to the product of transconductance and the input voltage.
$7.95 Integrated Circuit - SN74LS175, Quadruple D-Type Flip-Flops, 16-pin DIP This quad flip flop is a part used in our Relay True Bypass Switching Part 2: Momentary and Soft Touch Switches article. To read the full article and learn about a circuit for relay switching in stomp box effects, please see the following link. https://www.amplifiedparts.com/tech-articles/relay-true-bypass-switching-2 These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.$1.10
CMOS - CD4015, Dual 4-Stage Static Shift Register, 16-Pin DIP
CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line.
$0.75 CMOS - CD4017, CMOS Decade Counter, 16-Pin DIP CD4017B is a 5-stage Johnson counter having 10 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle.$0.55
CMOS - CD4021, 8-Stage Static Shift Register, 16-Pin DIP
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line.
$0.95 CMOS - CD4027, Dual J-K Flip-Flop, 16-Pin DIP CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the CD4013B dual D-type flip-flop. The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse.$0.65
CMOS - CD4029, Presettable Up/Down Counter, 16-Pin DIP
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low.
$0.75 CMOS - CD4040, 12-Stage Ripple-Carry Binary Counter/Divider, 16-Pin DIP The CD4040B is a 12-stage ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times.$0.59
CMOS - CD4046, Micropower Phase-Locked Loop, 16-Pin DIP
CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary. Features:
• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V
• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
• Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
• Choice of two phase comparators:
• Exclusive-OR network (I)
• Edge-controlled memory network with phase-pulse output for lock indication (II)
• High VCO linearity: <1% (typ.) at VDD = 10 V
• VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
• Source-follower output of VCO control input (Demod.
$1.29 CMOS - CD4049, Hex Inverting Buffer and Converter, 16-Pin DIP The CD4049UB devices are inverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features: • Inverting • High Sink Current for Driving 2 TTL Loads • High-to-Low Level Logic Conversion • 100% Tested for Quiescent Current at 20 V • Maximum Input Current of 1 µA at 18 V Over Full • Package Temperature Range; 100 nA at 18 V and 25°C • 5-V, 10-V, and 15-V Parametric Ratings Applications • CMOS to DTL or TTL Hex Converters • CMOS Current Sink or Source Drivers • CMOS High-to-Low Logic Level Converters$0.75
CMOS - CD4050, Hex Inverting Buffer and Converter, 16-Pin DIP
The CD4050B devices are noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) Features:
• Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
• Package Temperature Range; 100 nA at 18 V and 25°C
• 5-V, 10-V, and 15-V Parametric Ratings

Applications
• CMOS to DTL or TTL Hex Converters
• CMOS Current Sink or Source Drivers
• CMOS High-to-Low Logic Level Converters
$0.75 CMOS - CD4051, 8:1, 1-Channel Analog Multiplexer with Logic-Level Conversion, 16-Pin DIP The CD4051B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.$0.99
CMOS - CD4052, 4:1, 2-Channel General-Purpose Multiplexer, 16-Pin DIP
The CD4052B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.
$0.89 CMOS - CD4053, 2:1 SPDT, 3-Channel Analog Multiplexer with Logic-Level Conversion, 16-Pin DIP The CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.$0.75
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